The present invention relates to a configuration for efficiently laying out test elements for testing a semiconductor device at a semiconductor wafer level, and a test method using the test elements.
A TEG (Test Element Group) is used to ensure the reliability of a semiconductor device such as an integrated circuit. The evaluation of a process, circuit characteristics and reliability is performed by a characteristic evaluation (test) using the TEG. At the stage of product development, a reliability evaluation is conducted based on the result of measurement using the TEG, and a process or circuit design is modified or corrected based on the so-obtained result of evaluation. As to actual products, the reliability of each semiconductor device is evaluated to determine whether each of the produces is good.
Normally, electrical characteristic management TEGs are respectively disposed in scribed areas lying on a semiconductor wafer. Scribed lines for separating semiconductor chips individually are placed in the scribe areas respectively. Unless otherwise specified in particular, the scribe areas and the scribe lines are used in the same meaning in the following description. Further, unless otherwise specified in particular, slice lines and shut areas are also used in the same meaning as the scribe areas. Superimposition detection marks for mask alignment at a manufacturing process, thickness monitor marks and the like are also disposed in the scribe areas in large numbers except for the TEG.
With recent high integration in particular, there has been a tendency that the type of each utilized transistor and the number of wiring layers also increase and the numbers of superimposition marks and thickness monitoring marks increase. In the transistors, wirings and vias or the like increase, device's evaluation items to be managed increase, and the number of test elements for each TEG also increases correspondingly. There have heretofore been proposed various configurations/layouts for efficiently laying out such TEGs.
In a patent document 1 (Japanese Unexamined Patent Publication No. 2002-313864), electrode pads for TEG elements are disposed in scribe areas (scribe lines) respectively. TEGs are respectively disposed below electrode pads lying on semiconductor chips in alignment with the elected pads. As another embodiment, TEG elements are disposed in a layer below test electrode pads in association with the test electrode pads at the scribe lines. The TEG elements are of three-terminal elements. Three test electrode pads are disposed corresponding to the respective TEG elements. The TEG elements are electrically coupled to their corresponding test electrode pads. The layout area of each TEG is reduced by laying out the electrode pads and the TEG elements in overlaid form.
In a patent document 2 (Japanese Unexamined Patent Publication No. Hei 9 (1997)-199565), test electrode pads are disposed in a scribe area in zigzag form, and a test transistor is disposed below one test electrode pad layout area. The test transistor is of a four-terminal element. Four test electrode pads are disposed adjacent to each other corresponding to one test transistor. A control gate, a back gate, a source terminal and a drain terminal of the test transistor are electrically coupled to the four test electrode pads respectively disposed corresponding thereto.
In the patent document 2, the test electrode pads are disposed in each scribe area (scribe line) in zigzag form thereby to reduce the pitch between the test electrode pads and suppress an increase in the layout area of each test electrode pad. The test elements and the test electrode pads are disposed in superimposed form thereby to lay out a number of TEG elements on their corresponding scribe lines.
In a patent document 3 (Japanese Unexamined Patent Publication No. 2003-332397), test electrode pads are respectively placed in scribe lines so as to overlap with coupling metal wirings of test elements. Active regions of transistors that configure the test elements are alternately disposed in alignment with the test electrode pads and so as not to overlap therewith. The wirings for the test elements are disposed so as not to overlap with the electrode pads, thereby attaining the narrowing of the width of each scribe line.
When such TEG elements are disposed in large numbers, the pitch between the TEG elements becomes small. Hence, the interval between test probes also needs to be narrowed. Even when the pitch between such TEG elements becomes small, the reliable contact of the test probes with the test electrode pads is required to conduct high-reliable measurements.
A configuration aimed to bring such test probes into contact with the test electrode pads reliably has been described in a patent document 4 (Japanese Patent Publication No. Hei 5 (1993)-74882). In the configuration shown in the patent document 4, the test electrode pads are disposed around each semiconductor chip in alignment. Upon testing, test probe pins each having a pitch equal to twice the pitch between chip electrode pads is used. In this case, the test probe pins are divided into probe pins arranged in even-numbered electrode pads with respect to one chip, and probe pins coupled to odd-numbered electrode pads at each adjoining chip. After the completion of one test process, a probe card is moved by one chip on a semiconductor wafer, and the next test is executed. Thus, a test using the even-numbered test electrode pads is performed on one semiconductor chip. Then, a test using odd-numbered test electrode pads is performed thereon.
The patent document 4 aims to make the pitch between the test probe pins wider than the pitch between the electrode pads thereby to obtain the following advantageous effects. Even if wide probe pins each having rigidity are utilized, the contact between the probe pins can be avoided. Since the rigid probe pins are available, accurate measurements can be reliably made by causing the probe pins to contact their corresponding test electrode pads.
In a patent document 5 (Japanese Unexamined Patent Publication No. 2004-146415), a test probe card having a pin pitch equal to twice the pitch between test electrode pads is used. Testing is implemented while probe pins are being shifted by a test electrode pitch. The test electrode pads are disposed on a semiconductor chip in alignment. The patent document 5 aims to avoid that the pitch between pins of the test probe card becomes narrow, even in the case where the pitch between the test electrode pads becomes narrow.
In a patent document 6 (Japanese Utility Model Laid-Open No. Hei 4 (1992)-4754), testing is implemented while pins of a probe card are being brought into contact with alternate electrode pads lying on a semiconductor device. Each of input electrode pads is made larger than an output electrode pad in its layout area. In the probe card, probe pins are disposed with a pitch equal to twice the output electrode pads. Even when the probe pins are moved to their corresponding adjoining output electrode pads, the same voltage is applied to the input electrode pads. The patent document 6 aims to relax a condition for the pitch between the probe pins even when the pitch between the electrode pad rows becomes small.